Adding IEEE 754 floating-point support to an embedded-class processor presents a complex trade-off between performance, area, and implementation effort. This class explores these challenges through the design of an FPU for the NiosV processor (RISC-V RV32F), targeting FPGA platforms with hardened DSP blocks and vendor-provided soft floating-point primitives.

We examine the cost-benefit of implementing IEEE 754 features such as subnormals, flags, and rounding modes—often unused in embedded systems but impactful when deviating from the standard. Integration with integer-only cores is covered, including instruction decoding and pipeline interlocks.

The class follows a step-wise methodology, identifying high-impact decisions early to manage complexity throughout development. Topics include:

• Why soft microcontrollers on FPGAs, and why RISC-V?
• FPU design challenges and advantages for RISC-V
• Efficient use of FPGA DSP blocks for FP operations
• Leveraging vendor primitives for complex FP functions
• Integration challenges: missing ISA features, latency vs. frequency, concurrency
• Structured generation of FP functional units
• Occupancy tracking and flag generation techniques
• Trade-offs vs. RV32F and their impact on embedded applications
• Extending these techniques to build custom RISC-V extensions

Learning Outcomes:
1. Understand the architectural challenges and trade-offs involved in adding IEEE 754 floating-point support to embedded-class RISC-V processors.

2. Evaluate the benefits and limitations of implementing specific IEEE 754 features (e.g., subnormals, flags, rounding modes) in resource-constrained environments.

3. Leverage FPGA DSP blocks and vendor-provided primitives to efficiently implement core floating-point operations such as add, multiply, and fused multiply-add.

4. Design and integrate a custom FPU into an existing integer-only RISC-V core, addressing instruction decoding, pipeline interlocks, and concurrency.

5. Apply a step-wise methodology to manage complexity during hardware development and validation of floating-point units.

6. Track functional unit occupancy and manage latency/frequency trade-offs to optimise performance and area.

7. Assess compromises vs. RV32F compliance and understand their impact on embedded applications and system behaviour.

8. Explore techniques for building custom RISC-V extensions, enabling tailored compute capabilities for specific workloads.

Target Group:
FPGA Developers, RISC-V Architects, Embedded Systems and SoC Designers, Toolchain and Compiler Developers

Prior Knowledge:
1. FPGA Design Fundamentals
Understanding of FPGA architecture, synthesis flow, and basic HDL is essential.

2. RISC-V ISA Basics
Awareness of RISC-V instruction formats, RV32F extensions, and custom ISA capabilities.

3. IEEE 754 Floating Point Standard
Familiarity with floating-point representation, rounding modes, subnormals, and exception flags.

4. Processor Architecture and Design
Basic knowledge of processor pipelines, instruction decoding, and functional unit integration.

5. FPGA DSP Blocks
Understanding how to use DSP slices for arithmetic operations like multiply, add, and fused multiply-add.

6. Hardware-Software Co-Design Concepts

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